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Dot Matrix VHDL Course
Overview
Welcome (2:37)
How to use this course (4:11)
About the lectures (8:58)
Getting started
Purchasing the parts (13:25)
Using the Git repository (5:46)
Installing ModelSim and creating a project (8:53)
Installing Lattice iCEcube2 (6:18)
Installing VSCode with VHDL plugin (5:25)
Installing Tera Term (3:27)
Installing Fritzing (2:47)
Design overview
How dot matrix LED displays work (5:33)
Lattice iCEstick (8:31)
VHDL modules and dataflow (8:42)
LED resistor calculation (9:58)
LED driver (3:15)
The complete schematic (5:48)
Character buffer
Entity and outline of the module (12:28)
Instantiating the DUT in a testbench (8:42)
Creating the sampler process (5:46)
Clock and reset in the testbench (10:38)
Constants in packages (8:36)
ModelSim DO files (6:00)
Self-checking testbench using assert (12:20)
Exhaustive testing (8:36)
Checking the synthesis (11:19)
Read-only memory
How block RAM works in FPGAs (6:14)
Character map package (5:32)
Types package (8:25)
ROM module (7:56)
Setting up the testbench (9:30)
Subprograms package (11:12)
Looping over the input address (11:23)
Procedure for visualizing the matrix type (15:35)
Checking the synthesis (11:02)
Tcl scripting
Why you should learn Tcl (4:10)
Loading and running testbenches (5:29)
Regression testing (5:23)
Testbench FIFO
FIFOs and linked lists (4:49)
Declaring the protected type (6:56)
Record and access type (6:27)
The push procedure (6:18)
The pop function (5:59)
The peek and empty functions (3:28)
Testbench for the testbench FIFO (8:46)
Testing push, peek, and pop (11:02)
UART receiver
Defining the entity (4:45)
The finite-state machine (10:16)
Counting clock cycles (14:56)
Preliminary testbench (15:46)
Counting data bits (10:05)
Shift register (11:09)
The stop bit error output (9:50)
Checking the synthesis (11:22)
UART transmitter
Defining the entity (3:14)
The finite-state machine (5:25)
Sending the start bit (7:45)
Counter impure function (5:20)
Sending the data bits (7:36)
Sending the stop bit (4:03)
Adding the transmitter to the testbench (14:39)
Checking the synthesis (10:28)
UART self-checking testbench
Testbench strategy (4:24)
Transmit procedure (11:34)
Waiting until the transmitter is ready (3:59)
Testing all possible input values (9:47)
RX checker process (12:42)
Procedure for waiting until the FIFO is empty (5:59)
Checking the stop bit error output (12:14)
Reset
Why reset is an important subject (6:19)
Creating the reset module (9:13)
Testbench for the reset module (13:26)
Delaying by a delta cycle (6:54)
Verifying the duration of the reset strobe (12:10)
Simulate a reset button press (9:26)
Checking the synthesis (12:30)
LED controller
Defining the entity (4:59)
Defining the LED pulse time (9:21)
The row counter (6:31)
The row and column outputs (6:45)
Deadband period (8:34)
Assert statements for synthesis (7:16)
Checking the synthesis (9:13)
LED controller self-checking testbench
Testbench strategy (4:37)
Instantiating the DUT (9:52)
Speeding up the simulation (8:37)
Looping through all input characters (10:50)
Defining a verification component (10:08)
Instantiating the verification component (8:48)
Interfacing the verification component (6:05)
Printing the input and output character (11:11)
LED controller verification component
Modelling the dot matrix display (5:40)
Process for checking the pattern (11:16)
The touch_leds procedure (11:24)
The get_event function (11:37)
The to_matrix_type function (7:38)
The check_leds procedure 1 (12:51)
The check_leds procedure 2 (13:09)
Process for checking the pulse duration (11:16)
The check_pulse_time procedure (9:08)
The get_last_value and get_last_event functions (5:54)
Checking the pulse duration (9:26)
Checking the deadband duration (12:36)
Testing the testbench (6:57)
Top-level structural module
Top-level entity (13:01)
Instantiating the RTL modules (7:21)
Top-level signals (18:35)
The debug_leds module 1 (13:02)
The debug_leds module 2 (11:02)
Checking the synthesis (10:29)
Pin assignment and constraints (22:41)
Top-level testbench
Instantiating the DUT (12:04)
Instantiating the UART_TX module (10:10)
Instantiating the verification component (8:32)
The sequencer process (6:09)
The check_output procedure (14:44)
Self-checking testbench (12:58)
Interactive testbench (20:13)
Constructing the prototype
Soldering the iCEstick (3:08)
Converting a USB cable to a power supply (9:25)
Assembling the breadboard (7:12)
Testing the circuit (10:02)
Programming the FPGA (8:25)
Testing using Tera Term for sending data (6:58)
Fixing the mirrored characters (6:50)
Fixing the UART problem (4:17)
Congratulations! (2:09)
Testbench for the testbench FIFO
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