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Dot Matrix VHDL Course

From Idea Through Simulation to Implementation

Opens March 16, 2020

Course enrollment opens in

Enrollment opens on March 16, 18:00 UTC and closes on March 23, 18:00 UTC.

Are you learning VHDL? Do you still feel like you couldn’t manage an FPGA project on your own?

Learn what they don’t teach you at the university; how to create a real-world FPGA design from scratch to working prototype.

The Dot Matrix LED Controller FPGA Course teaches you proven VHDL methodologies that will increase your confidence as an FPGA engineer.

Trial and error is not a viable strategy when developing hardware. Learn how to structure your project and create a suite of self-checking testbenches as a professional FPGA engineer.

Get it right the first time you power on the chip.

The lectures teach you valuable skills for understanding how each code line translates into digital logic.

This course will take you from the beginner or intermediate level to being able to understand and use advanced VHDL coding constructs.


This is a hands-on course, meaning that we learn while creating something useful, not just theory and constructed examples. We are creating something very real, an FPGA controller capable of rendering characters on a dot matrix LED display.

Advanced VHDL Coding

Use the VHDL language to its full extent. Learn how to create dynamic data structures like protected types and access types; VHDL classes and pointers.

Let the language do most of the work by utilizing generics, VHDL signal attributes, and VHDL-2008 features.

Simulation Strategies

Create self-checking VHDL testbenches like a professional FPGA engineer by using packages, records, components, processes, functions, and procedures.

Divide and conquer complex testbenches by using verification components. Reuse them to save development time and cost.

Synthesis and Implementation

We will synthesize each module individually at the end of the sections, allowing you to understand what kind of logic every code line creates.

Finally, we will do the pin assignment and create clock constrains for the top module, before programming the FPGA.

Even though I’m a VHDL old-timer with 18 years of experience, I have found inspiration and new ideas from following the lectures.

I will introduce some of the concepts of modeling using advanced VHDL features in my project flow after taking this course.

I am particularly happy that the course follows a bottom-up approach in design, and that it teaches you to test each new module in depth before proceeding to the next. I also appreciate that the code for each lecture can be fetched from the included Git repository.

While other tutorials or learning resources focus on language syntax, this course teaches you how to approach a VHDL project.

The course is an investment for those who want to enter the FPGA design arena.

- Luca Colombini, Senior Design Engineer, CAEN

Like most classic programmers, I would have dived headfirst into a project and attempt to get things working mostly through trial and error. This method is fine for small projects in fast compiling languages, but in VHDL, not so much.

This course has taught me to take my time, especially with testing. A complete understanding of how all the modules fit together will give a much better and cleaner end result, and save a lot of time and stress on your part.

Jonas has taught me the importance of streamlining the design flow process with some neat tricks such as packages, self-checking testbenches and verification components (which from my experience, other FPGA engineers are unaware of).

Not only will this course teach you how to structure great quality VHDL code, but it will give you some general tools about how to check that the RTL is synthesizing correctly.

This course makes for an amazing head start introduction into the world of FPGA engineering. In areas like these, it is best to stay ahead of the curve and be thorough, as this will save you lots of time (and maybe money!) in the long run.

- Chris Hickling, PhD Student, Nuclear Fusion Physics at the University of Liverpool

The majority of tutorials and books teach you syntax, language constructs, and code patterns, but they don't motivate you to use them. For example, I’ve never used protected and access types before, even though I’ve read about them.

This course, on the other hand, presents a complex project and decomposes it into simple tasks. It uses a problem-oriented approach: raise the problem first and then solve it using the appropriate VHDL concepts.

It fills the gap between books and university programs that teach bare language constructs and code patterns without the experience of working on real-life projects.

I am usually very reluctant to pay for content, but trying to make sense of large and messy GitHub projects comes with headaches and pain. Here, on the other hand, all the course materials are presented with great care by clear and understandable explanation, clear language and high-quality video.

- Dymkov Mikhail

Analog Schematic

Early in the course, I will present the supporting analog schematic, as well as how dot matrix LED displays works.

As an FPGA engineer, you will have to know how to interpret analog schematics, not necessarily how to create them.

Breadboard Layout

You have the option to build your own prototype by purchasing the parts and following the instructions.

The detailed layout of the breadboard, as well as the schematic, can be examined in the free Fritzing software.

Lab Testing

In the last section of the course, we power on the prototype and send characters to it from the computer.

You will see that we have very few surprises when we finally do program the FPGA, thanks to our testbenches.

Course enrollment opens in

Enrollment opens on March 16, 18:00 UTC and closes on March 23, 18:00 UTC.

Course Curriculum



To my astonishment, it worked the first time we powered on the chip. How could it be?

It was my first serious FPGA project. Two of us were juniors, but the other half of this team of four were veterans who had been around programmable logic since the days of the EPROM PLDs. We had been developing this FPGA for almost a year, and this was the day the PCB arrived.

Now, imagine developing a software project for months and months, and having it working the first time you run the program. Not very likely. FPGA engineers don’t have the luxury of quick turnaround time, we have to hold our code to a higher standard.

Respin is not a word any project manager likes to hear.

Manufacturing PCBs is expensive and time-consuming. Not to mention the cost of a silicon respin, should your VHDL code be part of an ASIC project. Companies who engage in VHDL development all have strong demands for performance, that’s why they’re using FPGAs in the first place.

The FPGA which I was developing at the time was for an aerospace project. As you can imagine, the consequences would be dire if the FPGA malfunctioned as a result of a logic error. Still, I can sleep well at night with the knowledge of how robust our verification regime was.

You can only create what you can test.

This statement holds true in VHDL and FPGA development. That’s why most of the new features of the VHDL language are meant for testbenches, not for synthesis. The quality of your code is largely governed by how well your testbenches are performing.

For that reason, this course focuses heavily on testbenches and verification. The emphasis is on structuring your testbench suite in such a way that you never lose the overview, while at the same time enabling you to reuse code multiple places throughout the design.

Your Instructor


Jonas Julian Jensen
Jonas Julian Jensen

I’m Jonas Julian Jensen, an FPGA engineer from Norway. I earned my master’s degree in informatics at the University of Oslo. I wrote a thesis on acceleration of databases using dynamic reconfiguration in FPGAs. The thesis earned me a job as an FPGA engineer in Norway's top defense and aerospace company.

Today, I am running VHDLwhiz, the blog and tutorial website all about VHDL. I'm sharing the best of my methods, skills which has taken me years to learn, so that you can become productive as fast as possible.


Frequently Asked Questions


When does the course start and finish?
The course starts now and never ends! It is a completely self-paced online course - you decide when you start and when you finish.
How long do I have access to the course?
How does lifetime access sound? After enrolling, you have unlimited access to this course for as long as it exists - across any and all devices you own.
What if I am unhappy with the course?
We would never want you to be unhappy! If you are unsatisfied with your purchase, contact us in the first 30 days and we will give you a full refund.
Which parts do I need to build the prototype?
You can download the Bill of Materials (BOM) from here: http://bit.ly/DotMatrixBOM The cost depends on where you buy them from and if you have any parts and tools from before. We will talk about sourcing the parts in one of the first lectures in the course.
Do I need to do the physical implementation?
You can do the course as a simulation only exercise if you prefer to. You don’t need to purchase any hardware or even an FPGA development board. But you can create your own prototype if you want, all the information is included in the course. We’re only going to touch physical hardware in the last of the 16 sections in the course, before that we’ll be working in software tools. By creating a proper testbench suite, you will see that we get very few surprises when we finally do program the FPGA.
Can I use a different simulator, synthesis tool, or FPGA board?
I wouldn’t recommend using a different simulator or synthesis tool because they may behave slightly different, making it harder for you to follow the course. You won’t be able to follow my steps exactly. While the VHDL code should be portable, the TCL scripts use a few commands that are specific to ModelSim. The student version of the ModelSim VHDL simulator as well as the Lattice iCEcube2 FPGA software used in this course come with free licenses. All software tools used in this course can be downloaded free of charge.
What if I have a question before I buy?
Send an email to [email protected] and I will be happy to answer your questions.
Which software is used in this course?
Microsoft Windows 10, ModelSim PE Student Edition, Lattice iCEcube2 Design Software, Microsoft Visual Studio Code (VS Code), Tera Term, Fritzing, Git. Except for Windows 10, all software tools can be downloaded free of charge.
What are the prerequisites?
This course will take you from the beginner or intermediate level to being able to understand and use advanced VHDL coding constructs. It is suitable for the developer who has knowledge of other programming languages, but is new to VHDL and FPGAs. You should have at least eh basic understanding of what VHDL is and how FPGAs work to benefit from this course. For example, after completing my free Basic VHDL Tutorial series: https://vhdlwhiz.com/basic-vhdl-tutorials/
How is this course different from the Basic VHDL Tutorials series?
My free 23-part tutorial series found at https://vhdlwhiz.com/basic-vhdl-tutorials/ is for absolute beginners, while this course takes you from the beginner or intermediate level to being able to use advanced VHDL coding constructs. The Basic series is only about VHDL, while this course teaches you how to implement a real-life FPGA design. The Basic series focus on the simplest of VHDL syntax, while this course teaches you how to create hardware using VHDL like a professional FPGA engineer. The lecture videos in this course are paced at natural speed, which is slower than the sped-up videos of the Basic course. Finally, the detail level of this course is much higher, as it doesn't leave out any information needed to design, test, and build the physical prototype.
Why is the course available for purchase only a few weeks out of the year?
By batching sales to a few periods throughout the year, I am able better assist my students who will be going through the lectures roughly at the same time. The Dot Matrix course is a continuously evolving product. Based on feedback, I will be changing or adding content to the course between the launch periods. Once bought, you will have access to all future versions of the course, even if the price is raised at the next launch period.

Course enrollment opens in

Enrollment opens on March 16, 18:00 UTC and closes on March 23, 18:00 UTC.

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